The schematics are functionally complete.

It's nice when a project gets to point where there's a transition. The schematics for the NeXTretro are in SVN as of revision 27.(https://code.google.com/p/nextretro/)

There have been significant changes to the schematics; therefore, my previous posts regarding wiring are pretty much incorrect. The 68060 and 68040 have some pins with different behavior. The key pin is the /BG line, which is Bus Grant. That line determines which pins are which direction, and which ones are tri-stated.

/BR	/BG	/BB	notes
A	N	x	bidirectional lines inputs, so /TS /BB can be sampled
x	A	x	bidirectional lines outputs

This is the first system that I have every had to retrofit, and there are a few curiosities on the NeXT slab. First of all, the interrupt lines are all disabled on the 68040, and the snooping is disabled. The NeXT support ICs must do some sort of DMA through bus arbitration. I have tried to support all scenarios in the schematics, and I feel pretty good about them. A difference between the 68040 and the 68060 are the R/W line and the /TA line, as they are bidirectional on the 68040, and I use the R/W as if it was an 040.

The list of things to do now are as follows:

• Get a NeXT slab. First of all, the interrupt lines are all disabled on the 68040, and the snooping is disabled. The NeXT to get physical measurements for layout.
• Look at the software and see how many times the PTEST instruction shows up, and if I can modify the code to address it. I might have to disassemble and remake a ROM
• The schematics have a complete power block, but I need to revisit it for parts availability.
• The clock circuit is currently tied to the 25MHz bus; however, I have a circuit in my notes to make a clock multiplier so that I can get a 60MHz 060 on a 25Mhz bus.