Does the 68040 ever read the address lines?

I am confident that the NeXT slab's 68040 interface never reads the address lines. I would hate to be wrong, but the /MI line is floating and I do not see any evidence of cache snoop circuits. I wonder if some of the custom ICs off to the side also do caching. The schematics for the multiplexed bus should be in SVN as revision 10.

The biggest practical issue is that I'm not sure of the expected delays in the multiplexed bus. The Elmore delay model says that it will take awhile for the signals to go down the line for the latch. I've added a delay between the address and data enable just to try to be sure that no contention happens on the address/data drivers due to the fact that often state changes are not symmetric due to transistor behavior.