Getting the board into the socket... somehow.

I knew that finding someway to get a 179-pin board to board adapter was going to be difficult, but it seems to be impossible. I expect that if this works, there will be a total of 10 of these ever produced as a maximum, so I cannot really pay for tooling. I did find a bunch of little pins:
mill-max: 3117-2-00-21-00-00-08-0
I am not thrilled with the prospect of soldering 179 of them, aligned correctly, to the bottom of each board; however, that is what probably will happen.

The schematics are functionally complete.

It's nice when a project gets to point where there's a transition. The schematics for the NeXTretro are in SVN as of revision 27.(https://code.google.com/p/nextretro/)

There have been significant changes to the schematics; therefore, my previous posts regarding wiring are pretty much incorrect. The 68060 and 68040 have some pins with different behavior. The key pin is the /BG line, which is Bus Grant. That line determines which pins are which direction, and which ones are tri-stated.

/BR	/BG	/BB	notes
A	N	x	bidirectional lines inputs, so /TS /BB can be sampled
x	A	x	bidirectional lines outputs

This is the first system that I have every had to retrofit, and there are a few curiosities on the NeXT slab. First of all, the interrupt lines are all disabled on the 68040, and the snooping is disabled. The NeXT support ICs must do some sort of DMA through bus arbitration. I have tried to support all scenarios in the schematics, and I feel pretty good about them. A difference between the 68040 and the 68060 are the R/W line and the /TA line, as they are bidirectional on the 68040, and I use the R/W as if it was an 040.

The list of things to do now are as follows:

• Get a NeXT slab. First of all, the interrupt lines are all disabled on the 68040, and the snooping is disabled. The NeXT to get physical measurements for layout.
• Look at the software and see how many times the PTEST instruction shows up, and if I can modify the code to address it. I might have to disassemble and remake a ROM
• The schematics have a complete power block, but I need to revisit it for parts availability.
• The clock circuit is currently tied to the 25MHz bus; however, I have a circuit in my notes to make a clock multiplier so that I can get a 60MHz 060 on a 25Mhz bus.

All sorted out and ready to revisit the NeXTretro schematic!

The figure from the 68060 manual has a few typos, which I have corrected.

The signal updates are justified by:
TTx: 68060 Section 2.3.1, three state signals
/TA: 68060 Section 2.5.1, /TA is an input; whereas on the 68040 (sec 5.4.3) , it is tri-state, bidirectional signal

Excluding the clock, and power, here's what has to happen to make the 68060 act like a 68040.
1) /SNOOP held high, to mimic the SCx wiring on the 040.
2) /CLA is held high.
3) /BTT is held high so that the 060 acts as an 040.
4) /IPLx is held high so that there are no interrupts.
5) /AVEC is held high and disabled.
6) /TRA is GND and asserted for 040-style bus termination.

Excluding the address and data lines, the total are as follows:
input: 13
output: 9
bi-directional: 4

The 040 on the NeXT does not use the /TIP signal, but I will use that for my bus mux logic with the /TA signal. I will have a pull-up to /BB and use /BB and /BG to drive my outputs (060 section 2.7.2)

It looks like I am ready to revisit the schematics.

Tracking down typos.

My "interface" illustration:

And, I need to check TT0 and TA between the 040 and 060. TIP will be used for my select logic to set direction. All-in-all, outside of my "flow of conscience" posts, it's all coming together.

I have been checking all of my work for pin conditions. I have created a pin set illustration for the signals that are not floating below.

/IPLx: No interrupt requests (68040 manual table 8-3), pull-up, no other connections.
/AVEC: No auto vector (7.5.1.2) pull-up, no other connections.
/DLE: No data latch enable (5.11) pull-up high, no other connections.
SCx: No snooping (table 4.1) tied to gnd, no other connections.

/LOCK and /LOCKE are pulled high, but I think this is because of a reset state for the external ICs.

NeXT 68040 configuration

I've added the NeXT slab schematics to SVN. I've been trying to figure out why the LOCK and LOCKE lines would need pullup resistors if they bus never goes tristate. I think that it may be due to the other NeXT chipsets. I currently have a huge slew of glue logic that I am trying to minimize.

The pullup lines from the NeXT are in the following illustration.

The SIZ lines and R/W does not have pullups, so the only thing that makes sense is that the NeXT proprietary chipset does cause the 68040 to tristate the lines. I will have to look into this, because SC1,0 are both to GND.

Making better documentation.

I previously ranted about how I was unable to extract pictures from the MC68060 datasheet. I solved it with:

gs -q -dNOPAUSE -dBATCH -sDEVICE=pdfwrite -sOutputFile=Freescalecansukit.pdf -c .setpdfwrite -f MC68060UM.pdf

I am now able to make good documentation without recreating art!

68060 software package

The 68060 manual eludes to a "software package", which I found. The "DOS" versions did not have anything in them. They are 5k zipped. The sea.hqx file for a 68k Macintosh did have something, but what a hassle. Anyway, the mysterious 68060 software package is in SVN as of revision 14.

Glue Logic is a mess

A few modifications have been made in my notes, but are not yet in SVN. Section 7.11.1 in the 68060 manual describes the 68040-style arbitration. The biggest issue is handling all of the lines that are tristate due to all of the lever shifters. If I don't drive the level shifters, I will burn more current than I can get off the bus. I might have to put 1meg pulldowns.

Picking parts still.

Why use a $10 part when a $2 one will work? I've been picking parts for the past week when I have had free time to work on this. Trying to make sure that this project doesn't become too expensive to build.

Alternative level translators.

There are just so many voltages to move from 3.3 to 5! The key index word is not level shifter (that's too analog apparently), but "logic translator". I have some other candidate parts for the signals: SN74LVC8T245 and 74LVXC3245. You can pretty much take a "3" in any other suppliers parts and put a "T" in there for TIs.

The bidirectional signals are BB, TT0, TT1, TS. I'm rather confident that TS will never be an input because there's not cache snooping.

Power regulator schematic finished

Although there are some example regulators in the 68060 datasheet, I settled on a LTC1771-based regulator. I also will be changing many of the parts, which is a luxury that I have because I'm trying to build a single quality item instead of a million cell phones and shave pennies. I haven't picked all of the parts yet because it's a huge time sink.

Mangers: When picking parts, if you budget less than 1hr per part you are fooling yourselves.

Power schematic in SVN as of revision 11. Might be a few days before I get time to pick the parts.

68060 VDD

The manual keeps eluding to, and I keep ignoring, the fact that it seems you can power the 68060 off of a 5V IO voltage and a 3.3V core voltage; however, I've just assumed that you cannot. There are IVDD and EVDD pins on the 68060, but there's no documentation regarding them outside of the pinout. Nor is there power documentation.

11.12.1:
The MC68060 operates at a supply voltage of 3.3 V, not 5 V. The MC68060 interfaces gluelessly to transistor-transistor logic (TTL) levels.The following paragraphs discuss the two main issues of the lower, 3.3-V supply voltage.

Sounds eerily like I don't need my level shifters, but since I need to MUX the bus anyway, I might as well save a limited commodity. Perhaps they mean that the IO is 5V tolerant, which seems true via "12.4 DC ELECTRICAL SPECIFICATIONS".

Does the 68040 ever read the address lines?

I am confident that the NeXT slab's 68040 interface never reads the address lines. I would hate to be wrong, but the /MI line is floating and I do not see any evidence of cache snoop circuits. I wonder if some of the custom ICs off to the side also do caching. The schematics for the multiplexed bus should be in SVN as revision 10.

The biggest practical issue is that I'm not sure of the expected delays in the multiplexed bus. The Elmore delay model says that it will take awhile for the signals to go down the line for the latch. I've added a delay between the address and data enable just to try to be sure that no contention happens on the address/data drivers due to the fact that often state changes are not symmetric due to transistor behavior.

External logic from the 68060 to the NeXT 68040 socket.

I believe that I have the external logic required for the 68060 to the 68040 socket on the NeXT slab. I've picked the level shifter part, which is the 74ALVC164245 from ST. The TI sn74lvc16t245 will work as well.

Another thing that I determined is that the DLE line latch on the 68040 was wired to be transparent, so no worries there.

Timing diagram for the 68040 <-> 68060 interface.

The bus timings look like this:

I would like to take this time to mention that as I am trying to document this project, I have found that the 68060 manual is almost unusable. Why would anyone make a document which cannot be printed? I spent almost an hour trying to get a good image of the 68060 timing diagram. I eventually recreated it in Illustrator (took me all of 5 minutes). Freescale, you need people to use your ICs in new designs and this attitude is not helpful.

The greatest issue that I believe exists in making the 68060 compatible with the NeXT is the fact that the NeXT uses a multiplexed bus (which just gets my ire up. Saved a few bucks in the manufacture of a $10k computer and decreased the bus speed). The NeXT has CDIS low upon reset which sets the multiplexed bus mode. More importantly, there are different setup between the devices. 68060 manual 11.2.2 is a bit scary in this regard.

And the quote from 11.2.5:
The MC68060 does not implement the DLE functionality of the MC68040. Applications that use the DLE mode are not upgradable without using external logic.The MC68060 does not implement the muxed bus functionality of the MC68040. Applications that use muxed bus mode are not upgradable without using external logic.

The 68040 muxed mode is shown in the 68040 manual in Figure 7-46. /TS is low and /TA is high when the address is valid on the rising clock edge. Using the 68060, I am pretty sure that I can use BCLK to get the logic that I need to multiplex the bus. The 68060 manual has section 7.11.1 that is the 68040 arbitration protocol. I need to read through 7.11.1 and then figure out how to get the whole thing to come together.

Basically, I need to make figure 7-15 in the 68060 manual look like figure 7-46 in the 68040 manual.

68060 pin differences

Pins removed from 68060 when compared to the 68040, and their state in the socket on the Slab.

Pin Name	IO type	NeXT socket	Description
DLE	input	pullup	Data Latch Enable
SC1	input	GND	Snoop Control
SC0	input	GND	Snoop Control
BCLK	input	signal	Bus Clock
MI	output	float, NC	Inhibits memory devices from responding to an alternate master

Additional pins on the 68060.

Pin Name	IO type	Description
BS3	Z-output	D7-D0 selected in a long word transfer
BS2	Z-output	D15-D8 selected in a long word transfer
BS1	Z-output	D23-D16 selected in a long word transfer
BS0	Z-output	D31-D24 selected in a long word transfer
BS0	Z-output	D31-D24 selected in a long word transfer
CLKEN	input	defines clock speed of system bus
BGR	input	Bus Grant Rlinquish Control
TRA	input	Indicates the need to rerun the bus cycle
PST4	output	Indicates processor status
SAS	Z-output	starting termination acknowledge signal sampling
BTT	Z-bidirectional	bus tenure termination
SNOOP	input	alternate master logic snoop
THERM1	bidirectional	thermal resistor pin 1, 400ohm@25C
THERM0	bidirectional	thermal resistor pin 0
CLA	input	cycle long word address

And the good news is that the KiCad schematic components for the 68040 and 68060 are in the repository as of revision 4.

Starting out.

I have wanted to make a 68060 replacement for the 68040 for the NeXTStation for as long as I can remember. I have started this project about 3 times, and this time I want to make sure that it gets to the end. Therefore, I am documenting it as I go, and this blog will be my personal note board. I call the project: NeXTRetro. There's the pyro and nitro, so now the retro.

Everything that will encompass the project is here:

https://code.google.com/p/nextretro/

This should be fun!