Parts ordered!

The board components have all been ordered!
Now to just wait and find time to get things together.

Now to make packages.

I have a whole bunch of packages to make: TSSOP-48, TSSOP-8, TSSOP-16 and then all of the odd ones for the power supply. I hate the fact that I will not be up clocking the device, but I just cannot find good ICs for it. I might revisit this after I get the board laid out.

dead bug/live bug

I was not careful when looking at the 68040 documentation and the pinout is from the bottom. I need to update my sockets accordingly. I flipped things but I need to get things on grid. Initial changes as revision 44.

Working toward the layout.

This project has enjoyed undocumented bursts of work over the past few months. I have 15 minute bursts between DRC/LVS on my circuits. I'm trying to assemble my final part list so I can get an order in and make sure my footprints work. Revision 43 is in SVN.

How the NeXT Nitro Board worked.

I have designed what is basically a Nitro board for a NeXT; however, I am unable to get any of the parts that I would need to produce it.

From a schematic perspective, the important line is the TA line, which is the transfer acknowledge. The PCLK and the BCLK of the 68040 from the system does not affect the bus transfer, because the TA line is the slave acknowledge.

Consider a 68040 that is operating at 40MHz that is generated from the system PCLK. You attach a 40MHz cache between the MCU and the slower bus. You can use the cache as flow control for write-thru transfers where you complete the cache write and then mask the /TA line from the CPU with logic; however, you end up having to stall the MCU via the TA line until the read completes at the PCLK rate due to the slave ICs.

If I could get either TAG ICs or a 5v FPGA, the implementation would be fairly straight forward. I just cannot seem to get 5v parts anymore.

I wish I knew what the controller was doing

I designed a memory cache for the NeXT 68040; however, I really don't know if it will be useful because I do not know how the NeXT handles the bus. I have no way of knowing how many transfers are burst or synchronous, and how the controller is handling the TBI, TCI pins. (these are tied together) For these reasons, I'm going to shelve my cache for now and focus on getting the 68060 working.

SRAM cache looks like a possibility.

I am still looking at the system issues, but it looks like it is possible to get an external cache on the NeXT in the same way that the Nitro did. There are a few things that I am still looking into, such as if I can do some bus overclocking (relative to the NeXT bus). I found a document called the "MC68040 Designer's Handbook" that has an example cache scheme. Mine is a little different; however, it's good to know that my notes aligned with what Motorola did.

Handbook is in as of SVN rev 37.

exploding scope...

As most projects do, they explode in scope once you start thinking more about them. Once I decided that I could have a unified 040/060 socket, I then realized that I could add a cache. The issue is keeping the cost down; however, having 4 megs of cache on a system with 16-megs of memory would be a significant speedup. I will need to look at the cache flushing policies for NeXTStep.

unified socket.

I've been working so that I can reuse the 68060 board with 68040s. It will require soldering some resistors, but I believe that I can get it to work. I need to make the 68040 not be multiplexed because I want to keep the level shifters that will just shift 5V to 5V.

The two issues that I need to resolve is how to handle BCLK and /CDIS. I need to keep /CDIS high during reset so that it does not multiplex the bus. I will just use external logic to multiplex. I guess that I can just have a BCLK line waving around and making noise, but I would rather not. After I handle /CDIS, I will finish the clock circuit.

unified footprint for 040/060

I happen to have 40MHz 68040. I realized that with a few changes to the clock circuit, and adding a bypass, I can make my adapter also take a 68040 with the PCLK line at a higher speed. I will be modifying the schematics to reflect this change. It basically costs nothing as far as space.

I broke KiCad, and it won't compile

I didn't actually break KiCad, but my old Mac died that had it. The PC that I was using that had it just also died. All of this happened in time for my new mac to arrive, Japanese keyboard and all. （マクの日本語の入力がすごく好き）

I've been trying to get KiCad to compile, to no avail. I will have to put this off until I'm in a place where I get better 20k/sec in a few weeks. I have a windows xp disk around here somewhere, so I might just put it in vitualbox if I can find the install media.

Sockets started!

I've started on the foot prints for the ICs. You really don't realize how many pins 179 is until you go and actually make a socket.