Tuesday, February 18, 2014

How the NeXT Nitro Board worked.

I have designed what is basically a Nitro board for a NeXT; however, I am unable to get any of the parts that I would need to produce it.

From a schematic perspective, the important line is the TA line, which is the transfer acknowledge. The PCLK and the BCLK of the 68040 from the system does not affect the bus transfer, because the TA line is the slave acknowledge.

Consider a 68040 that is operating at 40MHz that is generated from the system PCLK. You attach a 40MHz cache between the MCU and the slower bus. You can use the cache as flow control for write-thru transfers where you complete the cache write and then mask the /TA line from the CPU with logic; however, you end up having to stall the MCU via the TA line until the read completes at the PCLK rate due to the slave ICs.

If I could get either TAG ICs or a 5v FPGA, the implementation would be fairly straight forward. I just cannot seem to get 5v parts anymore.

5 comments:

  1. How many gates do you need. Could a CPLD work?

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  2. FYI http://www.trenz-electronic.de/products/fpga-boards/oho-elektronik.html

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  3. Also check out the Atmel AT40K

    Digikey seems to have many in stock until March
    http://www.digikey.com/product-detail/en/AT40K05-2BQC/AT40K05-2BQC-ND/354784

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  4. I was looking at some of the Microsemi Igloo because they are FLASH based, and are FPGAs. I'm pretty sure that I'll need a FPGA. I'm still plugging along with the 68060 plan because the cache and the architecture will get me an equal speed improvement to the cache; however, this assumes my kernel patches will work.

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  5. I found these socket adapters which may be helpful for you:
    http://www.ebay.com/itm/2-x-PGA-179-S056-18D22-179-Pin-Adapter-Socket-with-gold-plated-Pin-E-tec-2pcs-/151088157527?pt=UK_BOI_Electrical_Components_Supplies_ET&hash=item232d8e5357

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