How the NeXT Nitro Board worked.

I have designed what is basically a Nitro board for a NeXT; however, I am unable to get any of the parts that I would need to produce it.

From a schematic perspective, the important line is the TA line, which is the transfer acknowledge. The PCLK and the BCLK of the 68040 from the system does not affect the bus transfer, because the TA line is the slave acknowledge.

Consider a 68040 that is operating at 40MHz that is generated from the system PCLK. You attach a 40MHz cache between the MCU and the slower bus. You can use the cache as flow control for write-thru transfers where you complete the cache write and then mask the /TA line from the CPU with logic; however, you end up having to stall the MCU via the TA line until the read completes at the PCLK rate due to the slave ICs.

If I could get either TAG ICs or a 5v FPGA, the implementation would be fairly straight forward. I just cannot seem to get 5v parts anymore.

I wish I knew what the controller was doing

I designed a memory cache for the NeXT 68040; however, I really don't know if it will be useful because I do not know how the NeXT handles the bus. I have no way of knowing how many transfers are burst or synchronous, and how the controller is handling the TBI, TCI pins. (these are tied together) For these reasons, I'm going to shelve my cache for now and focus on getting the 68060 working.