Oops, 68040 pin error

Thanks to Michal V, who pointed out that line D29 should be E16, and not F16. Now I have to see what I assigned to F16 since that's the address pin A9. I've had the parts for this sitting on my desk for over 6 months, and I haven't done much because of other semiconductor work, which took a lot longer than expected. 14nm takes up your work days, and your evenings. I hope to get a chance to get back to this project soon. Thanks again Michal V!

Google, things are around forever, right?

When I started on this project, two things happened:
1) I knew it'd take longer than I expect, but it's been way to long.
2) I figured that since #1 is true, I'd put everything into google code because it'd be around forever.

#2 turned out to not be true: as Google Code is shutting down.
This this reason, I wrote my own exporter/importer and I have moved my work locally to my servers. If anyone wants to take a look at what I'm doing, let me know and I'll attached a snapshot.

Parts ordered!

The board components have all been ordered!
Now to just wait and find time to get things together.

Now to make packages.

I have a whole bunch of packages to make: TSSOP-48, TSSOP-8, TSSOP-16 and then all of the odd ones for the power supply. I hate the fact that I will not be up clocking the device, but I just cannot find good ICs for it. I might revisit this after I get the board laid out.

dead bug/live bug

I was not careful when looking at the 68040 documentation and the pinout is from the bottom. I need to update my sockets accordingly. I flipped things but I need to get things on grid. Initial changes as revision 44.

Working toward the layout.

This project has enjoyed undocumented bursts of work over the past few months. I have 15 minute bursts between DRC/LVS on my circuits. I'm trying to assemble my final part list so I can get an order in and make sure my footprints work. Revision 43 is in SVN.

How the NeXT Nitro Board worked.

I have designed what is basically a Nitro board for a NeXT; however, I am unable to get any of the parts that I would need to produce it.

From a schematic perspective, the important line is the TA line, which is the transfer acknowledge. The PCLK and the BCLK of the 68040 from the system does not affect the bus transfer, because the TA line is the slave acknowledge.

Consider a 68040 that is operating at 40MHz that is generated from the system PCLK. You attach a 40MHz cache between the MCU and the slower bus. You can use the cache as flow control for write-thru transfers where you complete the cache write and then mask the /TA line from the CPU with logic; however, you end up having to stall the MCU via the TA line until the read completes at the PCLK rate due to the slave ICs.

If I could get either TAG ICs or a 5v FPGA, the implementation would be fairly straight forward. I just cannot seem to get 5v parts anymore.